The present invention relates to signal processing using time compressors, matched filters and correlators and more particularly to digital signal processing in which the signals are represented by a series of coded digits, for example digits found at the output of an analog-to-digital converter.
The linear and bilinear operations most needed for signal processing are: matched filtering, crosscorrelation, and the discrete Fourier transform. These transforms represent an excessive computational load for a general purpose computer and a heavy load even for a digital computer structured for signal processing. For example, a straight-forward linear transformation in a computer that takes a sequence of N data points into a sequence of N transform points may be regarded as a multiplication by a vector N.sup.2 matrix. A direct implementation that uses a single multiplier requires N.sup.2 multiplication times and N.sup.2 words of storage. The Fast Fourier Transform (FFT) offers some advantage in that it requires a number of multiplications proportional to Nlog.sub.2 N.
A number of transform implementations are known in the art that have a simple serial access data flow and a computation time proportional to N. These include the discrete Fourier transform (DFT), and transforms implemented using transversal filters as discussed in the paper by H. J. Whitehouse et at., "High Speed Serial Access Linear Transform Implementations", Naval Undersea Center, San Diego, CA 92132, January 1973. In general, apparatus in the prior art fall into two broad categories: those employing acoustic and nonacoustic means. Included in the former category are sonic, magnetostrictive, acoustic surface wave, and optacoustic filters while the latter category comprises charge coupled devices and binary shift registers. Acoustic filters have been described in the paper by W. D. Squire et al., "Linear Signal Processing and Ultrasonic Transversal Filters" appearing in the November, 1969, issue of IEEE Transactions on Microwave Theory and Techniques while nonacoustic filters have been described in the paper by G. W. Byram et al., "Signal Processing Device Technology" appearing in the Proceedings of the NATO Advanced Study Institute on Signal Processing held at the University of Technology, Loughborough, U.K. on Aug. 21 through Sept. 1, 1972.
As a rule, if interruptions of the processing are infrequent then acoustic filters are preferred since they offer large storage capacity, convenient tapping of delay lines, and low power dissipation. When short duration interruptions of the signal processing may occur then charge coupled devices (CCD) with their controllable clock rates offer the advantages of small size, offset only by charge transfer inefficiency and temperature sensitivity. When frequent processing interrupts are required, digital implementations in the form of shift registers are indicated. The rapid development of solid state technology however favors digital devices and these by far have now become available commercially.
Digital implementations in the present art have been obtained in the form of shift registers and these are described in the paper by J. J. Buie and D. R. Brewer, "A Large Scale Integrated Correlator" appearing in the October, 1972 issue of IEEE Journal of Solid State Circuits, SC-7. Such devices can be assembled from conventional medium scale integrated circuit logic or can be designed in large scale integrated (LSI) form. Thus, the digital implementation of a time compressor matched filter and correlator requires the high speed storage and readout of data as provided by a shift register. However, shift registers are limited in length and speed, and many similar devices are needed if much data must be stored. Metal-oxide substrate (MOS) registers, while providing high density, require extra power supplies and are slow speed when used as bipolar shift registers.
In many signal processing applications, the signals must be compressed in time. This is accomplished in the prior art by storing signals in a delay line and then retrieving them at a rate which is greater than the rate of storage, as explained in the article by Squire. Of particular interest is the delay line time compressor (DELTIC) which recirculates signals in a number of recirculations. The recirculation requires less length of delay line and therefore is a more efficient system.
In general, the prior digital art using shift registers utilize 2N words of storage and employ N multipliers for performing the correlation of signals. While the system of the present invention may also utilize 2N words of storage, its implementation of a digital DELTIC loop requires only a one word multiplier and in this manner provides new and improved time compressors, matched filters, and correlators while significantly decreasing the weight, size, power consumption, and cost for such devices.
From the discussion above it is clear that in the past, the digital implementation of a time compressor matched filter and correlator has been accomplished using shift registers in the memory element and, for all practical purposes, has not been successful for increasing the capacity and speed of operation for such devices beyond a certain limit determined by the technology of shift registers. Furthermore, the present art of digital implementations falls short when the size and cost of shift registers are considered in devices requiring high data throughputs.
It is the purpose of the present invention to produce a time compressor digital matched filter and correlator capable of exceeding the practical capacity and speed of present digital devices by at least one order of magnitude, at reduced size and cost.